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同大類學(xué)科其它級別期刊：
中科院 1區(qū) 期刊 JCR Q1 期刊 中科院 2區(qū) 期刊 JCR Q2 期刊 中科院 3區(qū) 期刊 JCR Q3 期刊 中科院 4區(qū) 期刊 JCR Q4 期刊Ieee Transactions On Very Large Scale Integration (vlsi) Systems SCIE
國際簡稱：IEEE T VLSI SYST 參考譯名：超大規(guī)模集成 (vlsi) 系統(tǒng)上的 Ieee 事務(wù)
主要研究方向：工程技術(shù)-工程：電子與電氣 非預(yù)警期刊 審稿周期： 一般,3-6周
《超大規(guī)模集成 (vlsi) 系統(tǒng)上的 Ieee 事務(wù)》(Ieee Transactions On Very Large Scale Integration (vlsi) Systems)是一本由Institute of Electrical and Electronics Engineers Inc.出版的以工程技術(shù)-工程：電子與電氣為研究特色的國際期刊，發(fā)表該領(lǐng)域相關(guān)的原創(chuàng)研究文章、評論文章和綜述文章，及時報道該領(lǐng)域相關(guān)理論、實踐和應(yīng)用學(xué)科的最新發(fā)現(xiàn)，旨在促進該學(xué)科領(lǐng)域科學(xué)信息的快速交流。該期刊是一本未開放期刊，近三年沒有被列入預(yù)警名單。該期刊享有很高的科學(xué)聲譽，影響因子不斷增加，發(fā)行量也同樣高。
- 2區(qū) 中科院分區(qū)
- Q2 JCR分區(qū)
- 241 年發(fā)文量
- 2.8 IF影響因子
- 未開放 是否OA
- 95 H-index
- 1993 創(chuàng)刊年份
- Bimonthly 出版周期
- English 出版語言
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
Ieee Transactions On Very Large Scale Integration (vlsi) Systems期刊信息
- ISSN：1063-8210
- 出版語言：English
- 是否OA：未開放
- E-ISSN：1557-9999
- 出版地區(qū)：UNITED STATES
- 是否預(yù)警：否
- 出版商：Institute of Electrical and Electronics Engineers Inc.
- 出版周期：Bimonthly
- 創(chuàng)刊時間：1993
- 開源占比：0.0933
- Gold OA文章占比：7.13%
- OA被引用占比：0
- 出版國人文章占比：0.15
- 出版撤稿占比：0
- 研究類文章占比：99.59%
Ieee Transactions On Very Large Scale Integration (vlsi) Systems CiteScore評價數(shù)據(jù)（2024年最新版）
| CiteScore | SJR | SNIP | CiteScore 指數(shù) | ||||||||||||||||
| 6.4 | 0.937 | 1.516 |
|
名詞解釋：CiteScore 是衡量期刊所發(fā)表文獻的平均受引用次數(shù)，是在 Scopus 中衡量期刊影響力的另一個指標。當(dāng)年CiteScore 的計算依據(jù)是期刊最近4年（含計算年度）的被引次數(shù)除以該期刊近四年發(fā)表的文獻數(shù)。例如，2022年的 CiteScore 計算方法為：2022年的 CiteScore =2019-2022年收到的對2019-2022年發(fā)表的文件的引用數(shù)量÷2019-2022年發(fā)布的文獻數(shù)量 注：文獻類型包括：文章、評論、會議論文、書籍章節(jié)和數(shù)據(jù)論文。
Ieee Transactions On Very Large Scale Integration (vlsi) Systems中科院評價數(shù)據(jù)
中科院 2023年12月升級版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 2區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 2區(qū) 3區(qū) |
中科院 2022年12月升級版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 2區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 3區(qū) 3區(qū) |
中科院 2021年12月舊的升級版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 3區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 3區(qū) 3區(qū) |
中科院 2021年12月基礎(chǔ)版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 4區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 4區(qū) 4區(qū) |
中科院 2021年12月升級版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 3區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 3區(qū) 3區(qū) |
中科院 2020年12月舊的升級版
| Top期刊 | 綜述期刊 | 大類學(xué)科 | 小類學(xué)科 | ||
| 否 | 否 | 工程技術(shù) | 2區(qū) | COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 計算機：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：電子與電氣 | 3區(qū) 3區(qū) |
Ieee Transactions On Very Large Scale Integration (vlsi) Systems JCR評價數(shù)據(jù)（2023-2024年最新版）
| 按JIF指標學(xué)科分區(qū) | 收錄子集 | 分區(qū) | 排名 | 百分位 |
| 學(xué)科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | SCIE | Q2 | 23 / 59 |
61.9% |
| 學(xué)科：ENGINEERING, ELECTRICAL & ELECTRONIC | SCIE | Q2 | 151 / 352 |
57.2% |
| 按JCI指標學(xué)科分區(qū) | 收錄子集 | 分區(qū) | 排名 | 百分位 |
| 學(xué)科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE | SCIE | Q2 | 26 / 59 |
56.78% |
| 學(xué)科：ENGINEERING, ELECTRICAL & ELECTRONIC | SCIE | Q2 | 149 / 354 |
58.05% |
Ieee Transactions On Very Large Scale Integration (vlsi) Systems歷年數(shù)據(jù)統(tǒng)計
影響因子
中科院分區(qū)
Ieee Transactions On Very Large Scale Integration (vlsi) Systems中國學(xué)者發(fā)文選摘
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1、A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
Author: Bai, Fujun; Wang, Song; Jia, Xuerong; Guo, Yixin; Yu, Bing; Wang, Hang; Lai, Cong; Ren, Qiwei; Sun, Hongbin
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 128-141. DOI: 10.1109/TVLSI.2022.3219437
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2、A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-mu W Embedded RRAM and Reconfigurable Strong PUF
Author: Ren, Qirui; Huo, Qiang; Chen, Zhisheng; Gao, Qi; Wang, Yiming; Yang, Yiming; Wu, Hao; Fu, Xiangqu; Xu, Xiaoxin; Luo, Qing; Gao, Jianfeng; Chen, Chengying; Zhao, Xiaojin; Lei, Dengyun; Wang, Xinghua; Zhang, Feng; Chen, Yong; Mak, Pui-In
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 243-252. DOI: 10.1109/TVLSI.2022.3222522
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3、A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique
Author: Wang, Yujia; Zhang, Jincheng; Chen, Yong; Ren, Junyan; Ma, Shunli
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 233-242. DOI: 10.1109/TVLSI.2022.3225967
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4、Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method
Author: Wang, Jun; Luo, Yuhuan; Guo, Wenting; Wu, Feng; Chu, Xiuqin
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 210-218. DOI: 10.1109/TVLSI.2022.3225533
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5、Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors
Author: Tan, Hongbing; Tong, Gan; Huang, Libo; Xiao, Liquan; Xiao, Nong
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 253-266. DOI: 10.1109/TVLSI.2022.3226185
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6、A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs
Author: Qiu, Lei; Meng, Tianyi; Yao, Bingbing; Du, Zihao; Yuan, Xiaohua
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 152-156. DOI: 10.1109/TVLSI.2022.3224237
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7、BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks
Author: Li, Hongyan; Lu, Hang; Wang, Haoxuan; Deng, Shengji; Li, Xiaowei
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 90-103. DOI: 10.1109/TVLSI.2022.3221732
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8、Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders
Author: Gao, Zhen; Shi, Jinchang; Liu, Qiang; Ullah, Anees; Reviriego, Pedro
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 142-146. DOI: 10.1109/TVLSI.2022.3224137
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